The present invention relates generally to integrated circuits, and, more particularly, to a current-starved inverter circuit.
A current-starved inverter is an inverter circuit that receives an input voltage and generates an inverted input voltage with a constant slew rate. Current-starved inverter circuits are commonly used as pre-driver circuits to control the switching of transmitters such as those used in a USB 2.0 high speed differential driver circuit. The output of the current-starved inverter circuit is used to control the slew rate of the high speed differential driver circuit.
FIG. 1 shows a schematic circuit diagram of a conventional current-starved inverter circuit 100. The current-starved inverter circuit 100 includes first and second transistors 102 and 104 and first and second current-mirror circuits 106 and 108. The first current-mirror circuit 106 is connected to first and second supply voltages VDD and VSS. In an example, the first supply voltage VDD is at 1.8 volts (V) and VSS is at ground level. The first current-mirror circuit 106 includes a first fixed-current source 110 and third and fourth transistors 112 and 114. The first fixed-current source 110 is connected to the second supply voltage VSS and generates a first reference current IREF—1. The third transistor 112 has a source terminal connected to the first supply voltage VDD, a gate terminal connected to its drain terminal, and the drain terminal is connected to the first fixed-current source 110. Since the gate terminal of the third transistor 112 is connected to its drain terminal, the third transistor 112 operates in saturation region. The fourth transistor 114 has a source terminal connected to the first supply voltage VDD, a gate terminal connected to the gate terminal of the third transistor 112, and a drain terminal connected to a source terminal of the first transistor 102. The fourth transistor 114 generates a first source current ISOURCE—1 based on the first reference current IREF—1. When the fourth transistor 114 operates in saturation region, the third and fourth transistors 112 and 114 form a current mirror causing the drain current of the third transistor 112, i.e., the first reference current IREF—1, to be mirrored to the fourth transistor 114. As a result, the first source current ISOURCE—1 that flows from the drain terminal of the fourth transistor 114 to the source terminal of the first transistor 102 is equal to the first reference current IREF—1. Since the first reference current IREF—1 is constant, the first source current ISOURCE—1 is constant.
The second current-mirror circuit 108 is connected to the first and second supply voltages VDD and VSS and includes a second fixed-current current source 116, and fifth and sixth transistors 118 and 120. The second current source 116 is connected to the first supply voltage VDD and generates a second reference current IREF—2. The fifth transistor 118 has a source terminal connected to the second supply voltage VSS, a gate terminal connected to its drain terminal, and the drain terminal is connected to the second fixed-current source 116. Since the gate terminal of the fifth transistor 118 is connected to its drain terminal, the fifth transistor 118 operates in saturation region. The sixth transistor 120 has a source terminal connected to the second supply voltage VSS, a gate terminal connected to the gate terminal of the fifth transistor 118, and a drain terminal connected to the source terminal of the second transistor 104. The sixth transistor 120 generates a first sink current ISINK—1 based on the second reference current IREF—2. When the sixth transistor 120 operates in the saturation region, the fifth and sixth transistors 118 and 120 form a current mirror causing the drain current of the fifth transistor 118, i.e., the second reference current IREF—2, to be mirrored to the sixth transistor 120. As a result, the first sink current ISINK—1 that flows from source terminal of the second transistor 104 to the drain terminal of the sixth transistor 120 is equal to the second reference current IREF—2. Since the second reference current IREF—2 is constant, the first sink current ISINK—1 is constant.
Gate terminals of the first and second transistors 102 and 104 receive the input voltage signal VIN. When the input voltage signal VIN is at the first supply voltage VDD level, the first transistor 102 is switched off and the second transistor 104 is switched on. When the second transistor 104 is switched on, the first sink current ISINK—1 flows from the drain terminal of the second transistor 104 to its source terminal and pulls down the drain terminal of the second transistor 104 to the second supply voltage VSS level. Thus, the inverted input voltage signal (i.e., the output voltage signal) VOUT—PA, which is generated at the drain terminal of the second transistor 104, is at the second supply voltage VSS when the input signal is at the first supply voltage VDD. When the input voltage signal VIN is at the second supply voltage VSS, the first transistor 102 is switched on and the second transistor 104 is switched off. When the first transistor 102 is switched on, the first source current ISOURCE—1 flows from the source terminal of the first transistor 102 to its drain terminal and pulls up the drain terminal of the first transistor 102 to the first supply voltage VDD level. Thus, the output voltage signal VOUT—PA, which is generated at the drain terminal of the first transistor 102, is at the first supply voltage VDD when the input voltage signal VIN is at the second supply voltage VSS.
FIG. 2 is a timing diagram that illustrates the input and output voltage signals VIN and VOUT—PA. At time T0, the input voltage signal VIN is at the second supply voltage VSS and the first source current ISOURCE—1 causes the output voltage signal VOUT—PA to ramp up. The first source current ISOURCE—1 remains constant until the output voltage signal VOUT—PA reaches a first threshold voltage level VTH1 (e.g. 1.3 V) at time T1. After T1, when the output voltage signal VOUT—PA exceeds the first threshold voltage level VTH1, the difference in voltage levels at the source and gate terminals (VSG) of the fourth transistor 114 and the source and drain terminals (VSD) of the fourth transistor 114 is greater than a threshold voltage (VTH). As a result, the fourth transistor 114 stops operating in the saturation region and starts operating in the linear region so the magnitude of the first source current ISOURCE—1 starts decreasing. Therefore, the time required for the output voltage signal VOUT—PA to reach the first supply voltage VDD is impacted. The output voltage signal VOUT—PA slowly reaches the first supply voltage VDD at time T2. At time T3, the input voltage signal VIN is at the first supply voltage VDD, the first transistor 102 is switched off and the second transistor 104 is switched on. The first sink current ISINK—1 causes the output voltage signal VOUT—PA to ramp down. The first sink current ISINK—1 remains constant until the output voltage signal VOUT—PA reaches a second threshold voltage level VTH2 (e.g., 0.75 V) at time T3.
After time T3, when the output voltage signal VOUT—PA is less the second threshold voltage level VTH2, the difference in voltage levels at the gate and source terminals (VGS) of the sixth transistor 120 and the drain and source terminals (VDS) of the sixth transistor 120 is greater than a threshold voltage (VTH). As a result, the sixth transistor 120 stops operating in the saturation region and starts operating in the linear region so the magnitude of the first sink current ISINK—1 starts decreasing. Therefore, the time for the output voltage signal VOUT—PA to reach the second supply voltage VSS increases. The output voltage signal VOUT—PA slowly reaches the second supply voltage VSS at time T4. Since the rise and fall times of the output voltage signal VOUT—PA do not match the rise and fall times of the input voltage signal VIN, the duty cycle of the output voltage signal VOUT—PA does not match the duty cycle of the input voltage signal VIN, thereby leading to duty cycle distortion. Further, if the frequency of the input voltage signal VIN is high, the output voltage signal VOUT—PA will fail to reach the first supply voltage VDD when the input voltage signal VIN is at second supply voltage VSS, and the second supply voltage VSS when the input voltage signal VIN is at first supply voltage VDD. As a result, the conventional current-starved inverter circuit 100 introduces inter-symbol interference (ISI), which causes data-dependent jitter (DDJ) in the data transmit path of the HS differential driver circuit. DDJ can induce errors in the output data stream of the differential driver circuit. Therefore, the conventional current-starved inverter circuit 100 suffers from bandwidth limitations and the output voltage signal VOUT—PA fails to provide a rail-to-rail voltage swing and a constant slew rate.
It would be advantageous to have a current-starved inverter circuit that generates an output voltage signal that has a constant slew rate and a rail-to-rail voltage swing.